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features ? high-performance, low-power atmel ? avr ? 8-bit microcontroller ? advanced risc architecture ? 133 powerful instructions ? mo st single clock cycle execution ? 32 x 8 general purpose working regist ers + peripheral control registers ? fully static operation ? up to 16mips throughput at 16mhz ? on-chip 2-cycle multiplier ? high endurance non-volatile memory segments ? 128kbytes of in-system self-pro grammable flash program memory ? 4kbytes eeprom ? 4kbytes internal sram ? write/erase cycles: 10,000 flash/100,000 eeprom ? data retention: 20 years at 85 c/100 years at 25 c (1) ? optional boot code section with independent lock bits in-system programming by on-chip boot program true read-while-write operation ? up to 64kbytes optional external memory space ? programming lock for software security ? spi interface for in-system programming ? qtouch ? library support ? capacitive touch buttons, sliders and wheels ? qtouch and qmatrix acquisition ? up to 64 sense channels ? jtag (ieee std. 1149.1 compliant) interface ? boundary-scan capabilities acco rding to the jtag standard ? extensive on-chip debug support ? programming of flash, eeprom, fuses and lock bits through the jtag interface ? peripheral features ? two 8-bit timer/counters with se parate prescalers and compare modes ? two expanded 16-bit timer/co unters with separate prescaler , compare mode and capture mode ? real time counter with separate oscillator ? two 8-bit pwm channels ? 6 pwm channels with programmable resolution from 2 to 16 bits ? output compare modulator ? 8-channel, 10-bit adc 8 single-ended channels 7 differential channels 2 differential channels with programmable gain at 1x, 10x, or 200x ? byte-oriented two-wire serial interface ? dual programmable serial usarts ? master/slave spi serial interface ? programmable watchdog timer with on-chip oscillator ? on-chip analog comparator ? special microcontroller features ? power-on reset and progra mmable brown-out detection ? internal calibrated rc oscillator ? external and intern al interrupt sources ? six sleep modes: idle, adc noise reduction, power-save, power-down, standby, and extended standby ? software selectable clock frequency ? atmega103 compatibility m ode selected by a fuse ? global pull-up disable ? i/o and packages ? 53 programmable i/o lines ? 64-lead tqfp and 64-pad qfn/mlf ? operating voltages ? 2.7 - 5.5v atmega128l ? 4.5 - 5.5v atmega128 ? speed grades ? 0 - 8mhz atmega128l ? 0 - 16mhz atmega128 8-bit atmel microcontroller with 128kbytes in-system programmable flash atmega128 atmega128l summary rev. 2467xs?avr?06/11
2 2467xs?avr?06/11 atmega128 pin configurations figure 1. pinout atmega128 note: the pinout figure applies to both tqfp and mlf packages. the bottom pad under the qfn/mlf package should be soldered to ground. overview the atmel ? avr ? atmega128 is a low-power cmos 8-bit microcontroller based on the avr enhanced risc architecture. by executing powerful instructions in a single clock cycle, the atmega128 achieves throughputs approaching 1mips per mhz allowing the system designer to optimize power consumption versus processing speed. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 4 8 47 46 45 44 43 42 41 40 39 3 8 37 36 35 34 33 pe n rxd0/(pdi) pe0 (txd0/pdo) pe1 (xck0/ai n 0) pe2 (oc3a/ai n 1) pe3 (oc3b/i n t4) pe4 (oc3c/i n t5) pe5 (t3/i n t6) pe6 (icp3/i n t7) pe7 (ss) pb0 (sck) pb1 (mosi) pb2 (miso) pb3 (oc0) pb4 (oc1a) pb5 (oc1b) pb6 pa3 (ad3) pa4 (ad4) pa5 (ad5) pa6 (ad6) pa7 (ad7) pg2(ale) pc7 (a15) pc6 (a14) pc5 (a13) pc4 (a12) pc3 (a11) pc2 (a10) pc1 (a9) pc0 (a 8 ) pg1(rd) pg0(wr) 64 63 62 61 60 59 5 8 57 56 55 54 53 52 51 50 49 17 1 8 19 20 21 22 23 24 25 26 27 2 8 29 30 31 32 (oc2/oc1c) pb7 tosc2/pg3 tosc1/pg4 reset v cc g n d xtal2 xtal1 (scl/i n t0) pd0 (sda/i n t1) pd1 (rxd1/i n t2) pd2 (txd1/i n t3) pd3 (icp1) pd4 (xck1) pd5 (t1) pd6 (t2) pd7 a v cc g n d aref pf0 (adc0) pf1 (adc1) pf2 (adc2) pf3 (adc3) pf4 (adc4/tck) pf5 (adc5/tms) pf6 (adc6/tdo) pf7 (adc7/tdi) g n d v cc pa0 (ad0) pa1 (ad1) pa2 (ad2)
3 2467xs?avr?06/11 atmega128 block diagram figure 2. block diagram program counter internal oscillator watchdog timer stack pointer program flash mcu control register sram general purpose registers instruction register timer/ counters instruction decoder data dir. reg. portb data dir. reg. porte data dir. reg. porta data dir. reg. portd data register portb data register porte data register porta data register portd timing and control oscillator oscillator interrupt unit eeprom spi usart0 status register z y x alu portb drivers porte drivers porta drivers portf drivers portd drivers portc drivers pb0 - pb7 pe0 - pe7 pa0 - pa7 pf0 - pf7 reset vcc agnd gnd aref xtal1 xtal2 control lines + - analog comparator pc0 - pc7 8-bit data bus avcc usart1 calib. osc data dir. reg. portc data register portc on-chip debug jtag tap programming logic pen boundary- scan data dir. reg. portf data register portf adc pd0 - pd7 data dir. reg. portg data reg. portg portg drivers pg0 - pg4 two-wire serial interface
4 2467xs?avr?06/11 atmega128 the atmel ? avr ? core combines a rich instruction set with 32 general purpose working regis- ters. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient wh ile achieving throughputs up to ten times faster than conventional cisc microcontrollers. the atmega128 provides the following features: 128kbytes of in-system programmable flash with read- w hile- w rite capabilities, 4kbytes eeprom, 4kby tes sram, 53 gene ral purpose i/o lines, 32 general purpose working registers, real time counter (rtc), four flexible timer/coun- ters with compare modes and p w m, 2 usarts, a byte oriented two-wire serial interface, an 8- channel, 10-bit adc with optional differential i nput stage with programmable gain, programma- ble w atchdog timer with intern al oscillator, an spi serial po rt, ieee std. 1149.1 compliant jtag test interface, also used for accessing the on-chip debug system and programming and six software selectable power saving modes. th e idle mode stops the cpu while allowing the sram, timer/counters, spi port, and interrupt system to continue functioning. the power-down mode saves the register c ontents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. in power-save mode, the asynchronous timer contin- ues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. the adc noise reduction mode stops the cp u and all i/o modules except asynchronous timer and adc, to minimize switching noise during adc conversions. in standby mode, the crystal/resonator oscillator is running while the re st of the device is sleeping. this allows very fast start-up combined with low power consumption. in extended standby mode, both the main oscillator and the a synchronous timer continue to run. atmel offers the qtouch ? library for embedding capacitive t ouch buttons, sliders and wheels functionality into avr microcontrollers. the patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys and includes adjacent key suppression ? (aks ? ) technology for unambiguous detection of key events. the easy-to-use qtouch suite toolchain allows you to explore, develop and debug your own touch applications. the device is manufactured using atmel?s high- density nonvolatile memory technology. the on- chip isp flash allows the prog ram memory to be repr ogrammed in-system th rough an spi serial interface, by a conventional nonvolatile memory programmer, or by an on-chip boot program running on the avr core. the boot program can use any interface to download the application program in the applicatio n flash memory. software in the boot flash section will continue to run while the application flash section is updated, providing true read- w hile- w rite operation. by combining an 8-bit risc cpu with in-system self-programmable flash on a monolithic chip, the atmel atmega128 is a powerful microcontroller that provides a highly flexible and cost effec- tive solution to many embedded control applications. the atmega128 device is supported with a full suite of program and system development tools including: c compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. atmega103 and atmega128 compatibility the atmega128 is a highly complex microcontroller where the number of i/o locations super- sedes the 64 i/o locations reserved in the avr instruction set. to ensure backw ard compatibility with the atmega103, all i/o locations present in atmega103 have the same location in atmega128. most additional i/o locations are added in an extended i/o space starting from $60 to $ff, (i.e., in the atmega103 internal ram space). these locations can be reached by using ld/lds/ldd and st/sts/std instructions only, not by using in and out instructions. the relo- cation of the internal ram space may still be a problem for atmega103 users. also, the increased number of interrupt vectors might be a problem if the code uses absolute addresses. to solve these problems, an atmega103 compatibility mode can be selected by programming the fuse m103c. in this mode, none of the functions in the extended i/o space are in use, so the internal ram is located as in atmega103. also, the extended interrupt vectors are removed.
5 2467xs?avr?06/11 atmega128 the atmega128 is 100% pin compatible with atmega103, and can replace the atmega103 on current printed circuit boards. the applic ation note ?replacing atmega103 by atmega128? describes what the user should be aware of replacing the atmega103 by an atmega128. atmega103 compatibility mode by programming the m103c fuse, the atmel ? atmega128 will be com patible with the atmega103 regards to ram, i/o pins and interrupt vectors as described above. however, some new features in atmega128 are no t available in this compatibility mode, these features are listed below: ? one usart instead of two, asynchronous mode only. only the eight least significant bits of the baud rate register is available. ? one 16 bits timer/counter with two compare registers instead of two 16-bit timer/counters with three compare registers. ? two-wire serial interface is not supported. ? port c is output only. ? port g serves alternate functions only (not a general i/o port). ? port f serves as digital input only in addition to analog input to the adc. ? boot loader capabilities is not supported. ? it is not possible to adjust the frequency of the internal calibrated rc oscillator. ? the external memory interface can not release any address pins for general i/o, neither configure different wait-states to different external memory address sections. in addition, there are some other minor differences to make it more compatible to atmega103: ? only extrf and porf exists in mcucsr. ? timed sequence not required for w atchdog time-out change. ? external interrupt pins 3 - 0 serve as level interrupt only. ? usart has no fifo buffer, so data overrun comes earlier. unused i/o bits in atmega103 should be written to 0 to ensure same operation in atmega128. pin descriptions vcc digital supply voltage. gnd ground. port a (pa7..pa0) port a is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port a output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port a pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port a pins are tri-stated when a reset condition becomes active, even if the clock is not running. port a also serves the functions of various special features of the atmega128 as listed on page 72 . port b (pb7..pb0) port b is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port b output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port b pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b also serves the functions of various special features of the atmega128 as listed on page 73 .
6 2467xs?avr?06/11 atmega128 port c (pc7..pc0) port c is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port c output buffers have symmetrical drive c haracteristics with bot h high sink and source capability. as inputs, port c pi ns that are externally pulled lo w will source current if the pull-up resistors are activated. the port c pins are tri-stated when a reset condition becomes active, even if the clock is not running. port c also serves the functions of special features of the atmel ? avr ? atmega128 as listed on page 76 . in atmega103 compatibility mode , port c is output only, and the port c pins are not tri- stated when a reset condition becomes active. note: the atmega128 is by default shipped in atmega103 compatibility mode. thus, if the parts are not programmed before they are put on the pcb, portc will be output during first power up, and until the atmega103 compatibility mode is disabled. port d (pd7..pd0) port d is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port d output buffers have symmetrical drive c haracteristics with bot h high sink and source capability. as inputs, port d pi ns that are externally pulled lo w will source current if the pull-up resistors are activated. the port d pins are tri-stated when a reset condition becomes active, even if the clock is not running. port d also serves the functions of various sp ecial features of the atmega128 as listed on page 77 . port e (pe7..pe0) port e is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port e output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port e pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port e pins are tri-stated when a reset condition becomes active, even if the clock is not running. port e also serves the functions of various special features of the atmega128 as listed on page 80 . port f (pf7..pf0) port f serves as the analog inputs to the a/d converter. port f also serves as an 8-bit bi-directional i/o port, if the a/d converter is not used. port pins can provide internal pull-up resistors (selected for each bit). the port f output buffers have sym- metrical drive characteristics with both high sink and source capa bility. as inputs, port f pins that are externally pulled low will source current if the pull-up resistors are ac tivated. the port f pins are tri-stated when a reset condition becomes active, even if the clock is not running. if the jtag interface is enabled, the pull-up resistors on pins pf7( tdi), pf5(tms), and pf4(tck) will be activated even if a reset occurs. the tdo pin is tri-stated unless tap states that shift out data are entered. port f also serves the functions of the jtag interface. in atmega103 compatibilit y mode, port f is an input port only. port g (pg4..pg0) port g is a 5-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port g output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port g pins that are extern ally pulled low will sour ce current if the pull-up resistors are activated. the port g pins are tri-stated when a reset condition becomes active, even if the clock is not running. port g also serves the functions of various special features. the port g pins are tri-stated when a reset condi tion becomes active, even if the clock is not running.
7 2467xs?avr?06/11 atmega128 in atmega103 compatibility mode, these pins only serves as strobes signals to the external memory as well as input to the 32khz oscillator, and the pins ar e initialized to pg0 = 1, pg1 = 1, and pg2 = 0 asynchronously when a reset condition becomes active, even if the clock is not running. pg3 and pg4 are oscillator pins. reset reset input. a low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. the minimum pulse length is given in table 19 on page 50 . shorter pulses are not guaranteed to generate a reset. xtal1 input to the inverting oscillato r amplifier and input to the in ternal clock operating circuit. xtal2 output from the invert ing oscillator amplifier. avcc avcc is the supply voltage pin for port f and the a/d converter. it should be externally con- nected to v cc , even if the adc is not used. if the adc is used, it should be connected to v cc through a low-pass filter. aref aref is the analog reference pin for the a/d converter. pen pen is a programming enable pin for the spi seri al programming mode, and is internally pulled high . by holding this pin low during a power-on reset, the device will enter the spi serial pro- gramming mode. pen has no function during normal operation.
8 2467xs?avr?06/11 atmega128 resources a comprehensive set of development tools, application notes, and datasheets are available for download on http:// www.atmel.com/avr. note: 1. data retention reliability qualification results show that the pr ojected data retention failure rate is much less than 1 ppm over 20 years at 85c or 100 years at 25c about code examples this datasheet contains simple code examples that briefly show how to use various parts of the device. these code examples assume that the part specific header file is included before compi- lation. be aware that not all c compiler vendors include bit definitions in the header files and interrupt handling in c is compiler dependent. please confirm with the c compiler documentation for more details. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructio ns that allow access to extended i/o. typically ?lds? and ?sts? combined with ? sbrs?, ?sbrc?, ?sbr?, and ?cbr?. capacitive touch sensing the atmel qtouch library provides a simple to us e solution to realize touch sensitive interfaces on most atmel avr microcontrollers. the qtouch library includes support for the qtouch and qmatrix acquisition methods. touch sensing can be added to any application by linking the appropriate atmel qtouch library for the avr microcontroller. this is done by using a simple set of apis to define the touch chan- nels and sensors, and then calling the touch sens ing api?s to retrieve the channel information and determine the touch sensor states. the qtouch library is free and downloadable from the atmel website at the following location: www.atmel.com/qtouchlibrary . for implementation details and other information, refer to the atmel qtouch library user guide - also available for download from the atmel website.
9 2467xs?avr?06/11 atmega128 instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adi w rdl,k add immediate to w ord rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbi w rdl,k subtract immediate from w ord rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd $ff ? rd z,c,n,v 1 neg rd two?s complement rd $00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? ($ff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd $ff none 1 mul rd, rr multiply unsigned r1:r0 rd x rr z,c 2 muls rd, rr multiply signed r1:r0 rd x rr z,c 2 mulsu rd, rr multiply signed with unsigned r1:r0 rd x rr z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 (rd x rr) << 1 z,c 2 fmuls rd, rr fractional multiply signed r1:r0 (rd x rr) << 1 z,c 2 fmulsu rd, rr fractional multiply signed with unsigned r1:r0 (rd x rr) << 1 z,c 2 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 jmp k direct jump pc knone3 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc znone3 call k direct subroutine call pc knone4 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1 / 2 / 3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1 / 2 / 3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1 / 2 / 3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1 / 2 / 3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1 / 2 / 3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1 / 2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1 / 2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1 / 2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1 / 2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1 / 2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1 / 2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1 / 2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1 / 2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1 / 2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1 / 2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1 / 2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1 / 2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1 / 2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1 / 2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1 / 2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1 / 2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1 / 2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1 / 2
10 2467xs?avr?06/11 atmega128 mnemonics operands description operation flags #clocks brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1 / 2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1 / 2 data transfer instructions mov rd, rr move between registers rd rr none 1 mov w rd, rr copy register w ord rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 elpm extended load program memory r0 (rampz:z) none 3 elpm rd, z extended load program memory rd (rampz:z) none 3 elpm rd, z+ extended load program memory and post-inc rd (rampz:z), rampz:z rampz:z+1 none 3 spm store program memory (z) r1:r0 none - in rd, p in port rd pnone1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1none2 cbi p,b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 s w ap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear ze ro flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 instruction set summary (continued)
11 2467xs?avr?06/11 atmega128 mnemonics operands description operation flags #clocks sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 w dr w atchdog reset (see specific descr. for w dr/timer) none 1 break break for on-chip debug only none n/a instruction set summary (continued)
12 2467xs?avr?06/11 atmega128 ordering information notes: 1. pb-free packaging complies to the european directive for restriction of hazardous substances (rohs directive). also halide free and fully green. 2. the device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering information and minimum quantities. 3. tape and reel speed (mhz) power supply ordering code (1) package (2) operation range 8 2.7 ? 5.5v atmega128l-8au atmega128l-8aur (3) atmega128l-8mu atmega128l-8mur (3) 64a 64a 64m1 64m1 industrial (-40 o c to 85 o c) 16 4.5 ? 5.5v atmega128-16au atmega128-16aur (3) ATMEGA128-16MU ATMEGA128-16MUr (3) 64a 64a 64m1 64m1 8 3.0 ? 5.5v atmega128l?8an atmega128l?8anr (3) atmega128l?8mn atmega128l?8mnr (3) 64a 64a 64m1 64m1 extended (-40 c to 105 c) 16 4.5 ? 5.5v atmega128?16an atmega128?16anr (3) atmega128?16mn atmega128?16mnr (3) 64a 64a 64m1 64m1 package type 64a 64-lead, 14 x 14 x 1.0mm, thin profil e plastic quad flat package (tqfp) 64m1 64-pad, 9 x 9 x 1.0mm, quad flat no -lead/micro lead frame package (qfn/mlf)
13 2467xs?avr?06/11 atmega128 packaging information 64a 2325 orchard parkway s an jose, ca 95131 title drawing no. r rev. 64a, 64-lead, 14 x 14 mm body s ize, 1.0 mm body thickness, 0. 8 mm lead pitch, thin profile plastic quad flat package (tqfp) c 64a 2010-10-20 pin 1 identifier 0~7 pin 1 l c a1 a2 a d1 d e e1 e b common dimen s ion s (unit of measure = mm) s ymbol min nom max note notes: 1.this package conforms to jedec reference m s -026, variation aeb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 15.75 16.00 16.25 d1 13.90 14.00 14.10 note 2 e 15.75 16.00 16.25 e1 13.90 14.00 14.10 note 2 b 0.30 ? 0.45 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0. 8 0 typ
14 2467xs?avr?06/11 atmega128 64m1 2325 orchard parkway s an jose, ca 95131 title drawing no. r rev. 64m1 , 64-pad, 9 x 9 x 1.0 mm body, lead pitch 0.50 mm, h 64m1 2010-10-19 common dimen s ion s (unit of measure = mm) s ymbol min nom max note a 0. 8 0 0.90 1.00 a1 ? 0.02 0.05 b 0.1 8 0.25 0.30 d d2 5.20 5.40 5.60 8 .90 9.00 9.10 8 .90 9.00 9.10 e e2 5.20 5.40 5.60 e 0.50 b s c l 0.35 0.40 0.45 notes: 1. jedec s tandard mo-220, ( s aw s ingulation) fig. 1, vmmd. 2. dimension and tolerance conform to a s mey14.5m-1994. top view s ide view bottom view d e marked pin# 1 id s eating plane a1 c a c 0.0 8 1 2 3 k 1.25 1.40 1.55 e2 d2 b e pin #1 corner l pin #1 triangle pin #1 chamfer (c 0.30) option a option b pin #1 notch (0.20 r) option c k k 5.40 mm exposed pad, micro lead frame package (mlf)
15 2467xs?avr?06/11 atmega128 errata the revision letter in this section refers to the revision of the atmega128 device. atmega128 rev. f to m ? first analog comparator conversion may be delayed ? interrupts may be lost when writing the timer registers in the asynchronous timer ? stabilizing time needed wh en changing xdiv register ? stabilizing time n eeded when changing osccal register ? idcode masks data from tdi input ? reading eeprom by using st or sts to set eer e bit triggers unexp ected interr upt request 1. first analog comparator conversion may be delayed if the device is powered by a slow rising v cc , the first analog comparator conversion will take longer than expected on some devices. problem fix/workaround w hen the device has been powered or reset, disable then enable theanalog comparator before the first conversion. 2. interrupts may be lost when writing the timer registers in the asynchronous timer the interrupt will be lo st if a timer register that is synchr onous timer clock is written when the asynchronous timer/counter register (tcntx) is 0x00. problem fix/workaround always check that the asynchronous timer/counter register neither have the value 0xff nor 0x00 before writing to the asynchronous timer control register (tccrx), asynchronous timer counter register (tcntx), or asynchronous output compare register (ocrx). 3. stabilizing time needed when changing xdiv register after increasing the source clock frequency more than 2% with settings in the xdiv register, the device may execute some of the subsequent instructions incorrectly. problem fix / workaround the nop instruction will always be executed correctly also right after a frequency change. thus, the next 8 instructions after the change s hould be nop instructions. to ensure this, follow this procedure: 1.clear the i bit in the sreg register. 2.set the new pre-scaling factor in xdiv register. 3.execute 8 nop instructions 4.set the i bit in sreg this will ensure that all subsequent instructions will execute correctly. assembly code example: cli ; clear global interrupt enable out xdiv, temp ; set new prescale value nop ; no operation nop ; no operation nop ; no operation nop ; no operation nop ; no operation nop ; no operation nop ; no operation nop ; no operation
16 2467xs?avr?06/11 atmega128 sei ; set global interrupt enable 4. stabilizing time needed when changing osccal register after increasing the source clock frequency more than 2% with settings in the osccal reg- ister, the device may execute some of the subsequent instructions incorrectly. problem fix / workaround the behavior follows errata number 3., and the same fix / w orkaround is applicable on this errata. 5. idcode masks data from tdi input the jtag instruction idcode is not working correctly. data to succeeding devices are replaced by all-ones during update-dr. problem fix / workaround ? if atmega128 is the only device in the scan chain, the problem is not visible. ? select the device id register of the atmega128 by issuing the idcode instruction or by entering the test-logic-reset state of the tap controller to read out the contents of its device id register and possibly data from succeeding devices of the scan chain. issue the bypass instructio n to the atmega128 while reading the device id registers of preceding devices of the boundary scan chain. ? if the device ids of all devices in the boundary scan chain must be captured simultaneously, the atmega128 must be the fist device in the chain. 6. reading eeprom by using st or sts to set eere bit triggers unexpected interrupt request. reading eeprom by using the st or sts command to set th e eere bit in the eecr reg- ister triggers an unexpecte d eeprom interrupt request. problem fix / workaround always use out or sbi to set eere in eecr.
17 2467xs?avr?06/11 atmega128 datasheet revision history please note that the referring page numbers in th is section are referred to this document. the referring revision in this section are referring to the document revision. rev. 2467x-06/11 1. corrected typos in ?ordering information? on page 12 . rev. 2467w-05/11 1. added atmel qtouch library support and qtouch sensing capability features. 2. updated ?dc characteristics? on page 318 . r rst maximum value changed from 60k to 85k . 3. updated ?ordering information? on page 12 to include tape & reel devices. rev. 2467v-02/11 1. updated the literature number (2467) that accidently changed in rev u. 2. editing update according to the atmel new style guide. no more space betweeen the numbers and their units. 3. reorganized the swapped chapters in rev u: 8-bit timer/counter 0, 16-bit tc1 and tc3, and 8-bit tc2 with pwm. rev. 2467u-08/10 1. updated ?ordering information? on page 12 . added ordering information for appen- dix a atmega128/l 105c. rev. 2467t-07/10 1. updated the ?usartn control and status register b ? ucsrnb? on page 189 . 2. added a link from ?minimizing power consumption? on page 47 to ?system clock and clock options? on page 35 . 3. updated use of technical terminology in datasheet 4. corrected formula in table 133, ?two-wire serial bus requirements,? on page 322 5. note 6 and note 7 below table 133, ?two-wire serial bus requirements,? on page 322 have been removed rev. 2467s-07/09 1. updated the ?errata? on page 15 . 2. updated the toc with the newest template (version 5.10). 3. added note ?not recommended from new designs? from the front page. 4. added typical i cc values for active and idle mode in ?dc characteristics? on page 318 . rev. 2467r-06/08 1. removed ?not recommended from new designs? from the front page.
18 2467xs?avr?06/11 atmega128 rev. 2467q-05/08 1. updated ?preventing eeprom corr uption? on page 24 . removed sentence ?if the detection level of the internal bod does not match the needed detection level, and external low v cc reset protection circuit can be used.? 2. updated table 85 on page 196 in ?examples of baud rate setting? on page 193 . remomved examples of frequencies above 16mhz. 3. updated figure 114 on page 238 . inductor value corrected from 10mh to 10h. 4. updated description of ?version? on page 253 . 5. atmega128l removed from ?dc characteristics? on page 318 . 6. added ?speed grades? on page 320 . 7. updated ?ordering information? on page 12 . pb-plated packages are no longer offered, and the ordering information for these packages are removed. there will no longer exist separ ate ordering codes for comm ercial operation range, only industrial operation range. 8. updated ?errata? on page 15 : merged errata description for rev.f to rev.m in ?atmega128 rev. f to m? . rev. 2467p-08/07 1. updated ?features? on page 1 . 2. added ?data retention? on page 8 . 3. updated table 60 on page 133 and table 95 on page 235 . 4. updated ?c code example (1) ? on page 176 . 5. updated figure 114 on page 238 . 6. updated ?xtal divide control register ? xdiv? on page 36 . 7. updated ?errata? on page 15 . 8. updated table 34 on page 76 . 9. updated ?slave mode? on page 166 . rev. 2467o-10/06 1. added note to ?timer/counter oscillator? on page 43 . 2. updated ?fast pwm mode? on page 124 . 3. updated table 52 on page 104 , table 54 on page 104 , table 59 on page 133 , table 61 on page 134 , table 64 on page 156 , and table 66 on page 157 . 4. updated ?errata? on page 15 .
19 2467xs?avr?06/11 atmega128 rev. 2467n-03/06 1. updated note for figure 1 on page 2 . 2. updated ?alternate functions of port d? on page 77 . 3. updated ?alternate functions of port g? on page 84 . 4. updated ?phase correct pwm mode? on page 100 . 5. updated table 59 on page 133 , table 60 on page 133 . 6. updated ?bit 2 ? tov3: timer/counter3, overflow flag? on page 141 . 7. updated ?serial peripheral interface ? spi? on page 162 . 8. updated features in ?analog to digital converter? on page 230 9. added note in ?input channel and gain selections? on page 243 . 10. updated ?errata? on page 15 . rev. 2467m-11/04 1. removed ?analog ground?, replaced by ?ground?. 2. updated table 11 on page 40 , table 114 on page 285 , table 128 on page 303 , and table 132 on page 321 . updated figure 114 on page 238 . 3. added note to ?port c (pc7..pc0)? on page 6 . 4. updated ?ordering information? on page 12 . rev. 2467l-05/04 1. removed ?preliminary? and ?tbd? from the datasheet, replaced occurrences of icx with icpx. 2. updated table 8 on page 38 , table 19 on page 50 , table 22 on page 56 , table 96 on page 242 , table 126 on page 299 , table 128 on page 303 , table 132 on page 321 , and table 134 on page 323 . 3. updated ?external memory interface? on page 25 . 4. updated ?device identification register? on page 253 . 5. updated ?electrical characteristics? on page 318 . 6. updated ?adc characteristics? on page 325 . 7. updated ?typical characteristics? on page 333 . 8. updated ?ordering information? on page 12 . rev. 2467k-03/04 1. updated ?errata? on page 15 .
20 2467xs?avr?06/11 atmega128 rev. 2467j-12/03 1. updated ?calibrated internal rc oscillator? on page 41 . rev. 2467i-09/03 1. updated note in ?xtal divide control register ? xdiv? on page 36 . 2. updated ?jtag interface and on-chip debug system? on page 48 . 3. updated values for v bot (bodlevel = 1) in table 19 on page 50 . 4. updated ?test access port ? tap? on page 246 regarding jtagen. 5. updated description for the jtd bit on page 255 . 6. added a note regarding jtagen fuse to table 118 on page 288 . 7. updated r pu values in ?dc characteristics? on page 318 . 8. added a proposal for solving problems regarding the jtag instruction idcode in ?errata? on page 15 . rev. 2467h-02/03 1. corrected the names of the two prescaler bits in the sfior register. 2. added chip erase as a first step under ?programming the flash? on page 315 and ?programming the eeprom? on page 316 . 3. removed reference to the ?multipurpose oscillator? application note and the ?32khz crystal oscillator? application note, which do not exist. 4. corrected ocn waveforms in figure 52 on page 125 . 5. various minor timer1 corrections. 6. added information about pwm symmetry for timer0 and timer2. 7. various minor twi corrections. 8. added reference to table 124 on page 291 from both spi serial programming and self programming to inform about the flash page size. 9. added note under ?filling the temporary buffer (page loading)? on page 280 about writing to the eeprom during an spm page load. 10. removed adhsm completely. 11. added section ?eeprom write during power-down sleep mode? on page 24 . 12. updated drawings in ?packaging information? on page 13 . rev. 2467g-09/02 1. changed the endurance on the flash to 10,000 write/erase cycles. rev. 2467f-09/02 1. added 64-pad qfn/mlf package and updated ?ordering information? on page 12 .
21 2467xs?avr?06/11 atmega128 2. added the section ?using all locations of external memory smaller than 64 kbyte? on page 32 . 3. added the section ?default clock source? on page 37 . 4. renamed spmcr to spmcsr in entire document. 5. when using external clock there are some limitations regards to change of frequency. this is descried in ?external clock? on page 42 and table 131, ?external clock drive,? on page 320 . 6. added a sub section regarding ocd-system and power consumption in the section ?minimizing power consumption? on page 47 . 7. corrected typo (wgm-bit setting) for: ?fast p w m mode? on page 98 (timer/counter0). ?phase correct p w m mode? on page 100 (timer/counter0). ?fast p w m mode? on page 151 (timer/counter2). ?phase correct p w m mode? on page 152 (timer/counter2). 8. corrected table 81 on page 191 (usart). 9. corrected table 102 on page 259 (boundary-scan) 10. updated vil parameter in ?dc characteristics? on page 318 . rev. 2467e-04/02 1. updated the characterization data in section ?typical characteristics? on page 333 . 2. updated the following tables: table 19 on page 50 , table 20 on page 54 , table 68 on page 157 , table 102 on page 259 , and table 136 on page 328. 3. updated description of osccal calibration byte. in the data sheet, it was not explained how to take advantage of the calibration bytes for 2mhz, 4mhz, and 8mhz oscillator selections. th is is now added in t he following sections: improved description of ?oscillator calibration regi ster ? osccal? on page 41 and ?cali- bration byte? on page 289 . rev. 2467d-03/02 1. added more information about ?atmega103 compatibility mode? on page 5 . 2. updated table 2, ?eeprom progra mming time,? on page 22 . 3. updated typical start-up time in table 7 on page 37 , table 9 and table 10 on page 39 , table 12 on page 40 , table 14 on page 41 , and table 16 on page 42 . 4. updated table 22 on page 56 with typical wdt time-out. 5. corrected description of adsc bit in ?adc control and status register a ? adcsra? on page 244 .
22 2467xs?avr?06/11 atmega128 6. improved description on how to do a polarity check of the adc differential results in ?adc conversion result? on page 241 . 7. corrected jtag version numbers in ?jtag version numbers? on page 256. 8. improved description of addressing during spm (usage of rampz) on ?addressing the flash during self-programming? on page 278 , ?performing page erase by spm? on page 280 , and ?performing a page write? on page 280 . 9. added not regarding ocden fuse below table 118 on page 288 . 10. updated programming figures: figure 135 on page 290 and figure 144 on page 301 are updated to also reflect that avcc must be connected during programming mode. figure 139 on page 297 added to illustrate how to program the fuses. 11. added a note regarding usage of the prog_pageload and prog_pageread instructions on page 307 . 12. added calibrated rc oscillator characterization curves in section ?typical charac- teristics? on page 333 . 13. updated ?two-wire serial interface? section. more details regarding use of the t w i power-down operation and using the t w i as master with low t w brr values are added into the data sheet. added the note at the end of the ?bit rate generator unit? on page 203 . added the description at the end of ?address match unit? on page 204 . 14. added a note regarding usage of timer/counter0 combined with the clock. see ?xtal divide control register ? xdiv? on page 36 . rev. 2467c-02/02 1. corrected description of alternate functions of port g corrected description of tosc1 and tosc2 in ?alternate functions of port g? on page 84 . 2. added jtag version numbers for rev. f and rev. g updated table 100 on page 256. 3 added some preliminary test li mits and characterization data removed some of the tbd's in the following tables and pages: table 19 on page 50 , table 20 on page 54 , ?dc characteristics? on page 318 , table 131 on page 320 , table 134 on page 323 , and table 136 on page 328. 4. corrected ?ordering information? on page 12 . 5. added some characterization data in section ?typical characteristics? on page 333 .. 6. removed alternative algortihm for leaving jtag programming mode. see ?leaving programming mode? on page 315. 7. added description on how to access the extended fuse byte through jtag pro- gramming mode.
23 2467xs?avr?06/11 atmega128 see ?programming the fuses? on page 317 and ?reading the fuses and lock bits? on page 317 .
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